1. Technical Field
The present invention relates generally to a semiconductor apparatus, and more particularly, to a reset signal generation apparatus.
2. Related Art
A semiconductor apparatus performs an initialization operation before a normal operation, and prepares for the normal operation. In order to perform the initialization operation, the semiconductor apparatus receives a command signal from an external source for instructing the initialization operation, or generates a reset signal according to a signal generated therein. In order to stably perform the initialization operation, the reset signal may be normally generated.
FIG. 1 is a diagram schematically illustrating the configuration of a reset signal generation circuit 10 in a conventional art. The conventional reset signal generation circuit 10 receives a reset command signal RSTC for instructing an initialization operation, and sequentially delays the reset command signal RSTC through an inverter chain 11. Then, the reset signal generation circuit 10 logically combines the delayed reset command signals through a NAND gate 12, and generates a low pulse type signal. Furthermore, the reset signal generation circuit 10 increases a pulse width of the low pulse type signal through strength adjustments by a driver 13, a capacitor 14, and the like, thereby finally generating a reset signal RSTB.
As described above, the conventional reset signal RSTB is generated through a plurality of delay elements. However, since the plurality of delay elements is affected by PVT variation, a pulse width of the reset signal may not be sufficiently ensured due to an external voltage level and skew. When the pulse width of the reset signal is not sufficient, internal circuits for performing a normal operation are not normally initialized, resulting in an erroneous operation and a defected semiconductor apparatus.